Соловьев Роман Александрович
Московский институт электроники и математики им. А.Н. Тихонова
Должности
- Профессор — Московский институт электроники и математики им. А.Н. Тихонова, Департамент компьютерной инженерии
Био
- · Начал работать в НИУ ВШЭ в 2025 году.
- · Научно-педагогический стаж: 20 лет.
Образование
- 2018 · Доктор наук
- 2007 · Кандидат наук
Идентификаторы исследователя
- ORCID:
0000-0003-0312-452X - ResearcherID:
I-3618-2014 - SPIN РИНЦ:
5508-2076 - Google Scholar: https://scholar.google.ru/citations?user=pu9Zix8AAAAJ
- Scopus AuthorID:
56535303500
Публикации (8)
Generation of Synthesizable Verilog Code From Natural Language Specifications
2026 · ARTICLE · en
This study presents a method for generating synthesizable Verilog code for digital integrated circuits directly from natural-language specifications. The approach combines large language models with parameter-efficient fine-tuning (specifically, Low-Rank Adaptation and Quantized Low-Rank Adaptation) together with a specialized corpus of specification-code pairs that covers common design patterns and varying task complexity. The pipeline includes automated compilation, simulation, and synthesizability checks to ensure that outputs are both syntactically correct and suitable for downstream tool flows. Evaluation is performed using the pass-at-k metric on the standardized VerilogEval benchmark. The fine-tuned models substantially improve functional correctness over untuned baselines, achieving task-level pass@3 of up to 0.88 on a controlled VerilogEval dataset, while reducing both syntax and logic errors. The results indicate that reliable Verilog code generation from natural language can be achieved under constrained compute budgets; in our setup, effective training and inference remained feasible on a single graphics processing unit. Beyond empirical gains, the method demonstrates practical value for design automation by shortening iteration cycles and lowering the effort needed to move from textual requirements to synthesizable hardware modules. Overall, the findings support the use of large language models, paired with targeted data and validation, as a viable pathway for Verilog code generation and for accelerating the development of complex digital devices.
Machine Learning Methods for Fast Evaluation of Static IR Drop Effect
2026 · ARTICLE · en
With the continuous scaling of semiconductor design technologies, evaluating static IR drop has become a critical bottleneck in the physical synthesis flow. This paper presents a machine learning-based framework that transforms the power delivery network (PDN) analysis problem into an image-to-image translation task using a U-Net architecture with MaxViT and EfficientNet encoders. By implementing a novel SPICE-to-image conversion flow and an asymmetric loss function, our method achieved a Top 3 ranking in the ICCAD 2023 Contest (Problem C). The experimental results demonstrate that the proposed model achieves a Mean Absolute Error (MAE) below 15×10(−5) V while providing up to a 30× speedup compared to NGSPICE.
MinMAE calibration method for convolutional neural network quantization
2026 · ARTICLE · en
This article introduces MinMAE, a novel activation calibration method for Post-Training Quantization (PTQ) that significantly reduces accuracy loss in Convolutional Neural Networks (CNN). Motivated by the need for high-fidelity quantization without costly retraining, MinMAE directly minimizes the Mean Absolute Error (MAE) between original and dequantized activations, making it robust to outliers that degrade standard methods. We evaluated MinMAE against absmax and mean+3std on YOLOv8n and YOLOv8s models. For 8-bit quantization on YOLOv8n, MinMAE achieved 8.4% mean Average Precision (mAP) loss, whereas standard methods led to drops of up to 14.4%. On the larger YOLOv8s model, MinMAE also demonstrated superior performance, reducing loss from 7.2% to just 5.2%. While this approach requires a higher one-time calibration time, the substantial accuracy gains establish MinMAE as a highly effective and broadly applicable strategy for improving the stability and performance of quantized CNNs.
PAGR: Accelerating Global Routing for VLSI Design Flow
2025 · ARTICLE · en
In this paper, we present PAGR (Python Alpha Global Routing) – a solution to the global routing problem in physical synthesis based on data from the ISPD 2024 contest. Our solution constructs a weighted graph and builds a Steiner tree. To accelerate the Steiner tree search, we propose a technique for the graph size minimization by reducing the input 3D matrix. This method slightly decreases result quality but finds solutions 2–10 times faster. We also detail our methods for parallel calculations and computing graph edge weights. Experimental results show that while the current Python implementation does not achieve high routing speeds, the solution’s quality measured in contest metrics (wire length, via, overflow) is comparable to top contestants. Implementing the algorithm in C/C++ will significantly improve runtime. The algorithm’s description can benefit future research, and the source code with detailed comments is available online.
Reduction Method for a Network-on-Chip Low-Level Modeling
2025 · ARTICLE · en
This article explores the concept of low-level modeling of networks-on-chip (NoCs). A method for reducing the low-level NoC model by replacing the real IP blocks with a data packet generator module is proposed. This makes it possible to significantly increase the maximum number of nodes in the simulated NoC, as well as speed up the modeling and investigate the resource costs for network synthesis. A universal interface that can be used to connect new components to the network is also described. This interface has two main benefits: it reduces connection resource costs by eliminating the need to modify the connected component and shortens the time required to configure the connection interface itself. The proposed methodology of low-level NoC modeling is shown to be effective in analyzing the operation of routing algorithms of the NoC communication subsystem based on various topologies.
Parallel Multi-Level Simulation for Large-Scale Detailed Intelligent Transportation System Modeling
2025 · ARTICLE · en
Nowadays, the problems of traffic accidents, inefficiency, and congestion still affect transportation systems. Conventional solutions often do not resolve and can even exacerbate the problems. Intelligent transportation system (ITS) technology, including intelligent vehicles, could provide a solution for these problems. However, such technologies should be thoroughly verified and validated before their large-scale adoption. Computer simulation can be used for this task to avoid the expenses of real-world testing. Modern consumer hardware computers are not powerful enough to handle large-scale scenes with high detail. Therefore, a parallel simulation approach employing multiple computers, each processing a separate scene of limited size, is proposed. To define the requirements for a suitable simulation tool, the needs of ITS simulation and Digital Twin technology are discussed, and existing simulation environments suitable for ITS technology verification and validation are evaluated. Further, an architecture for a parallel and multi-level simulation environment for large-scale detailed ITS modeling is proposed. The proposed integrated simulation environment uses the nanoscopic CARLA and microscopic SUMO simulators to implement multi-level and parallel nanoscopic simulation by creating a large scene on the microscopic simulation level and combining the information from multiple parallelly executed nanoscopic scenes. Special handling for nanoscopic scene logic is proposed using a concept of Buffer Zones that allows traffic participants to perceive environmental information beyond the logical boundary of the scene they belong to. The proposed approaches are demonstrated in a series of experiments as a proof of concept and are integrated into the CAVISE simulation environment.
The Third Visual Object Tracking Segmentation VOTS2025 Challenge Results
2025 · CHAPTER · en
The VOTS2025 is the third edition of the Visual Object Tracking Segmentation benchmark. Organised the VOT initiative, VOTS builds on 10 years of experience in organising VOT challenges. Building on the tracking setup introduced in VOTS2023, the challenge continues to integrate short-term and long-term tracking, as well as single-target and multi-target scenarios, using segmentation masks as the sole form of target annotation. This year's benchmark features three sub-challenges. VOTS2025 and VOTSt2025, evaluate tracking of conventional objects and objects undergoing topological changes, respectively. A new addition, VOTS-RT2025, aims to foster the development of efficient tracking models by introducing constraints that highlight realtime performance. All sub-challenges adopt a consistent evaluation protocol, with VOTS-RT2025 introducing specific modifications to reflect latency-aware performance. We report and analyze results from 32 submissions. Full tracker descriptions, source code, datasetsand the evaluation toolkit are available on the project website https://www.votchallenge.net/vots2025/.
AlphaDent: A dataset for automated tooth pathology detection
2025 · ARTICLE · en
In this article, we present a new unique dataset for dental research – AlphaDent. This dataset is based on the DSLR camera photographs of the teeth of 295 patients and contains over 1200 images. The dataset is labeled for solving the instance segmentation problem and is divided into 9 classes. The article provides a detailed description of the dataset and the labeling format. The article also provides the details of the experiment on neural network training for the Instance Segmentation problem using this dataset. The results obtained show high quality of predictions. The dataset is published under an open license; and the training/inference code and model weights are also available under open licenses.
Курсы (0)
Нет курсов.